Static Timing Analysis

Project : OLED
Build Time : 10/06/23 16:52:17
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 3.30
VDDABUF : 3.30
VDDD : 3.30
VDDIO0 : 3.30
VDDIO1 : 3.30
VDDIO2 : 3.30
VDDIO3 : 3.30
VUSB : 3.30
Voltage : 3.3
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyBUS_CLK(fixed-function) CyBUS_CLK(fixed-function) 24.000 MHz 24.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
CyScBoostClk CyScBoostClk 12.000 MHz 12.000 MHz N/A
+ Clock To Output Section
+ CyBUS_CLK(fixed-function)
Source Destination Delay (ns)
\I2COLED:I2C_FF\/scl_out SCL(0)_PAD:out 25.877
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2COLED:I2C_FF\ \I2COLED:I2C_FF\/clock \I2COLED:I2C_FF\/scl_out 1.000
Route 1 \I2COLED:Net_643_0\ \I2COLED:I2C_FF\/scl_out SCL(0)/pin_input 9.075
iocell2 P0[1] 1 SCL(0) SCL(0)/pin_input SCL(0)/pad_out 15.802
Route 1 SCL(0)_PAD SCL(0)/pad_out SCL(0)_PAD:out 0.000
Clock Clock path delay 0.000
\I2COLED:I2C_FF\/sda_out SDA(0)_PAD:out 25.681
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2COLED:I2C_FF\ \I2COLED:I2C_FF\/clock \I2COLED:I2C_FF\/sda_out 1.000
Route 1 \I2COLED:sda_x_wire\ \I2COLED:I2C_FF\/sda_out SDA(0)/pin_input 9.430
iocell1 P0[0] 1 SDA(0) SDA(0)/pin_input SDA(0)/pad_out 15.251
Route 1 SDA(0)_PAD SDA(0)/pad_out SDA(0)_PAD:out 0.000
Clock Clock path delay 0.000